1. Field of the Invention
This invention relates to cache coherence protocols and, more particularly, to software-based cache coherence protocols.
2. Description of the Related Art
Shared memory multiprocessor systems typically include a large block of random access memory that can be accessed by each of the central processing units (CPUs) of the system. One issue with shared memory systems is cache coherence. Whenever one cache is updated with information that may be used by other processors, the change needs to be communicated to the other processors, otherwise the different processors may begin working with incoherent data.
Multiprocessor cache coherence is typically done in fixed hardware state machines. However, fixed hardware solutions limit the flexibility of cache coherence protocols. To enable more flexible cache coherence, a programmable coherence processor may be employed instead of hardware state machines. However, both the fixed and programmable coherence engines are costly solutions since they typically require dedicated hardware to perform the cache coherence operations.